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MITSUBISHI MICROCOMPUTERS
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 38C2 group is the 8-bit microcomputer based on the 740 family core technology. The 38C2 group has an LCD drive control circuit, a 10-channel A-D converter, and a Serial I/O as additional functions. The various microcomputers in the 38C2 group include variations of internal memory size and packaging. For details, refer to the section on part numbering.
FEATURES
qBasic machine-language instructions ....................................... 71 qThe minimum instruction execution time .......................... 0.25 s (at 8MHz oscillation frequency) qMemory size ROM ................................................................ 16 K to 60 K bytes RAM ................................................................. 640 to 2048 bytes qProgrammable input/output ports ............................................. 51 (common to SEG: 24) qInterrupts ................................................... 18 sources, 16 vectors qTimers ............................................................ 8-bit 4, 16-bit 2 qA-D converter ................................................. 10-bit 8 channels qSerial I/O ........................ 8-bit 2 (UART or Clock-synchronized) qPWM .................. 10-bit 2, 16-bit 1 (common to IGBT output)
qLCD drive control circuit Bias ................................................................................... 1/2, 1/3 Duty ........................................................................... 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ........................................................................ 24 qTwo clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) qWatchdog timer ............................................................... 8-bit 1 q LED direct drive port .................................................................. 8 (average current: 15 mA, peak current: 30 mA, total current: 90 mA) qPower source voltage In through mode .......................................................... 4.0 to 5.5 V (at 8 MHz oscillation frequency) In frequency/2 mode ................................................... 1.8 to 5.5 V (at 4 MHz oscillation frequency, A-D operation excluded) In low-speed mode ..................................................... 1.8 to 5.5 V (at 32 kHz oscillation frequency) qPower dissipation In through mode ................................................................. 26 mW (at 8 MHz oscillation frequency, VCC = 5 V) In low-speed mode ............................................................. 21 W (at 32 kHz oscillation frequency, VCC = 3 V) qOperating temperature range ................................... - 20 to 85C
PIN CONFIGURATION (TOP VIEW)
P04/SEG4 P05/SEG5 P06/SEG6 P07/SEG7 P10/SEG8 P11/SEG9 P12/SEG10 P13/SEG11 P14/SEG12 P15/SEG13 P16/SEG14 P17/SEG15 P20/SEG16 P21/SEG17 P22/SEG18 P23/SEG19
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
(KW7)/P03/SEG3 (KW6)/P02/SEG2 (KW5)/P01/SEG1 (KW4)/P00/SEG0 (KW3)/P57/SRDY1 (KW2)/P56/SCLK1 (KW1)/P55/TXD1 (KW0)/P54/RXD1 P53/T4OUT/PWM1 P52/T3OUT/PWM0 P51/INT1 P50/INT0 AVSS VREF P47/RTP1/AN7 P46/RTP0/AN6
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
M38C2XMX-XXXFP
25 24 23 22 21 20 19 18 17
P24/SEG20 P25/SEG21 P26/SEG22/VL1 P27/SEG23/VL2 VL3 COM0 COM1 COM2 COM3 P30/SRDY2/(LED0) P31/SCLK2/(LED1) P32/TXD2/(LED2) P33/RXD2/(LED3) P34/INT2/(LED4) P35/TXOUT/(LED5) P36/T2OUT//(LED6)
Package type : 64P6N-A/64P6Q-A
Fig. 1 M38C2XMX-XXXFP pin configuration
P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/OOUT1/AN1 P40/OOUT0/AN0 CNVSS RESET P62/XCOUT P61/XCIN VSS XIN XOUT VCC P60/CNTR1 P37/CNTR0/(LED7)
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FUNCTIONAL BLOCK DIAGRAM
P
8
8 8 8
IM REL
Fig. 2 Functional block diagram
Port P2 (8) Port P3 (8) Timer Timer X (16 bits) XIN-XOUT (Main clock) XCIN-XCOUT (Sub-clock) PWM (16 bits) IGBT output Timer Y (16 bits) Timer 1 (8 bits) Timer 2 (8 bits) Timer 3 (8 bits) PWM0 (10 bits) Timer 4 (8 bits) PWM1 (10 bits) System clock generation
Port P0 (8)
Port P1 (8)
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Y NAR
Internal peripheral function
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A-D conversion
10-bit 8-channel
Serial I/O
Serial I/O1
(UART or Clock synchronous)
Serial I/O2
(UART or Clock synchronous)
Memory ROM CPU core
RAM for LCD display (12 bytes)
LCD drive control circuit
4 COM 24 SEG
RAM
Watchdog timer
Port P4 (8)
8 3
Port P5 (8) Port P6 (3)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C2 Group
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1) Pin VCC, VSS VREF AVSS RESET XIN Name Power source Analog reference voltage Analog power source Reset input Clock input Function * Apply voltage of 1.8 V to 5.5 V to VCC, and 0 V to VSS. * Reference voltage input pin for A-D converter. * GND input pin for A-D converter. Connect to VSS. * Reset input pin for active "L." * Input and output pins for the main clock generating circuit. * Feedback resistor is built in between XIN pin and XOUT pin. * Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. When an external clock is used, connect the clock source to XIN, and leave XOUT pin open. * Input 0 VL1 VL2 VL3 VCC voltage. * Input 0 - VL3 voltage to LCD. * LCD common output pins. * COM2 and COM3 are not used at 1/2 duty ratio. * COM3 is not used at 1/3 duty ratio. * 8-bit I/O port. * LCD segment output pins * CMOS compatible input level. * CMOS 3-state output structure. * I/O direction register allows each port to be individually programmed as either input or output. * Pull-up control is enabled. * Key input interrupt pins Function except a port function
XOUT
Clock output
VL3 COM0 - COM3 P00/SEG0 - P03/SEG3 P04/SEG4 - P07/SEG7 P10/SEG8 - P17/SEG15 P20/SEG16 - P25/SEG21 P26/SEG22/VL1 P27/SEG23/VL2 P30/SRDY2 P31/SCLK2 P32/TxD2 P33/RxD2 P34/INT2 P35/TXOUT P36/T2OUT/ P37/CNTR0 P40/OOUT0/AN0 P41/OOUT1/AN1 P42/AN2- P45/AN5 P46/RTP0/AN6 P47/RTP1/AN7 P50/INT0 P51/INT1 P52/T3OUT/PWM0 P53/T4OUT/PWM1 P54/RxD1 P55/TxD1 P56/SCLK1 P57/SRDY1
LCD power source Common output
I/O port P0
I/O port P1 I/O port P2
* LCD power source input pins I/O port P3 * Serial I/O2 function pins
* External interrupt pin * Timer X, Timer 2 output pins * Timer X function pin * AD converter input * Oscillation external output pins pins
I/O port P4
* Real time port function pins I/O port P5 * External interrupt pins * * * * Timer 3, Timer 4 output pins PWM output pins Serial I/O1 function pins Key input interrupt input pins
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 2 Pin description (2) Pin P60/CNTR1 P61/XCIN P62/XCOUT Name I/O port P6 Function Function except a port function
CNVSS
CNVSS
* 3-bit I/O port. * Timer Y function pin * CMOS compatible input level. * I/O pins for sub-clock generating circuit. * CMOS 3-state output structure. Connect oscillators to them. * I/O direction register allows each pin to be individually programmed as either input or output. * Pull-up control is enabled. * VPP power input pin in the flash mode. When MCU is operating, connect to VSS.
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M38C2
9
M
C-
XXX
HP
Package type FP : 64P6N-A package HP : 64P6Q-A package
ROM number Omitted in Flash memory version.
Characteristics - : Standard D : Extended operating temperature version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes
9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.
Memory type M : Mask ROM version F : Flash memory version
RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 3 Part numbering
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 38C2 group as follows.
Packages
64P6Q-A ..................................... 0.5 mm-pitch plastic molded QFP 64P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
Memory Type
Support for mask ROM, Flash-memory versions
Memory Size
ROM/flash memory size ...................................... 16 K to 60 K bytes RAM size ............................................................. 640 to 2048 bytes
Memory Expansion Plan
ROM size (bytes) 60K 56K 48K 40K 32K 28K 24K 20K 16K 12K 8K 4K
Under development
Under development
M38C29FF
Under development
M38C29MC
M38C24M6
Under development
M38C24M4
192 256
384
512
640
768
896
1024
1536
2048
RAM size (bytes) Products under development or planning : the development schedule and specification may be revised without notice.
Fig. 4 Memory expansion plan Currently supported products are listed below. Table 3 Support products Product name M38C29MC-XXXFP M38C29MC-XXXHP M38C24M6-XXXFP M38C24M6-XXXHP M38C24M4-XXXFP M38C24M4-XXXHP M38C29FFFP M38C29FFHP ROM size (bytes) ROM size for User in ( ) 49152 (49022) 24576 (24446) 16384 (16254) 61440 (61310) RAM size (bytes) 2048 640 640 2048 Package 64P6N-A 64P6Q-A 64P6N-A 64P6Q-A 64P6N-A 64P6Q-A 64P6N-A 64P6Q-A Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Flash memory version Flash memory version As of May 2000
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 38C2 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0" , the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.
b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL
b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag
NVTBD I ZC
Fig. 5 740 Family CPU register structure
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) - 1 (PCL) (S)- 1
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S) - 1 (PCL) (S) - 1 (PS) (S) - 1 Push contents of processor status register on stack Push return address on stack
Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S)
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S)
I Flag is set from "0" to "1" Fetch the jump vector
POP contents of processor status register from stack
POP return address from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is "1" Interrupt disable flag is "0"
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack PHA Accumulator PHP Processor status register
Pop instruction from stack PLA PLP
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor Status Register (PS)]
The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. * Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. * Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". * Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". * Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
* Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". * Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. * Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. * Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - -
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the control bit for the internal system clock. The CPU mode register is allocated at address 003B16.
b7
b0 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area Not used (returns "1" when read) (Do not write "0" to this bit.) Main clock (XIN-XOUT) division ratio selection bits b5 b4 0 0 : XIN/8 (frequency/8 mode) 0 1 : XIN/4 (frequency/4 mode) 1 0 : XIN/2 (frequency/2 mode) 1 1 : XIN (through mode) System clock control bits b7 b6 0 0 : XIN stop, XCIN oscillating, system clock = XCIN 0 1 : XIN oscillating, XCIN stop, system clock = XIN 1 0 : XIN oscillating, XCIN oscillating, system clock = XCIN 1 1 : XIN oscillating, XCIN oscillating, system clock = XIN
Fig. 7 Structure of CPU mode register
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
000016 RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 ROM ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
Fig. 8 Memory map diagram
SFR area LCD display RAM area Zero page
RAM
004016 004C16 010016
XXXX16 Reserved area 084016 0FE016 100016 YYYY16 Reserved ROM area (128 bytes) ZZZZ16 Not used SFR area
Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
FF0016
FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area
Special page
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 Clock output control register (CKOUT) 001916 A-D control register (ADCON) 001A16 A-D conversion register (low-order) (ADL) 001B16 A-D conversion register (high-order) (ADH) 001C16 Transmit/receive buffer register 1 (TB1/RB1) 001D16 Serial I/O1 status register (SIO1STS) 001E16 Transmit/receive buffer register 2 (TB2/RB2) 001F16 Serial I/O2 status register (SIO2STS) 0FE016 Serial I/O1 control register (SIO1CON) 0FE116 UART1 control register (UART1CON) 0FE216 Baudrate generator 1 (BRG1) 0FE316 Serial I/O2 control register (SIO2CON) 0FE416 UART2 control register (UART2CON) 0FE516 Baudrate generator 2 (BRG2) 0FE616 0FE716 0FE816 0FE916 0FEA16 0FEB16 0FEC16 0FED16 0FEE16 0FEF16
002016 Timer 1 (T1) 002116 Timer 2 (T2) 002216 Timer 3 (T3) 002316 Timer 4 (T4) 002416 PWM01 register (PWM01) 002516 Timer 12 mode register (T12M) 002616 Timer 34 mode register (T34M) 002716 002816 Compare register (low-order) (COMPL) 002916 Compare register (high-order) (COMPH) 002A16 Timer X (low-order) (TXL) 002B16 Timer X (high-order) (TXH) 002C16 Timer X (extension) (TXEX) 002D16 Timer Y (low-order) (TYL) 002E16 Timer Y (high-order) (TYH) 002F16 Timer X mode register (TXM) 003016 Timer Y mode register (TYM) 003116 003216 003316 003416 003516 003616 003716 Watchdog timer control register (WDTCON) 003816 LCD power control register (VLCON) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) 0FF016 Oscillation output control register (OSCOUT) 0FF116 PULL register (PULL) 0FF216 Key input control register (KIC) 0FF316 Timer 1234 mode register (T1234M) 0FF416 Timer X control register (TXCON) 0FF516 Timer 12 frequency division selection register (PRE12) 0FF616 Timer 34 frequency division selection register (PRE34) 0FF716 Timer XY frequency division selection register (PREXY) 0FF816 Segment output disable register 0 (SEG0) 0FF916 Segment output disable register 1 (SEG1) 0FFA16 Segment output disable register 2 (SEG2) 0FFB16 Timer Y mode register 2 (TYM2) 0FFC16 0FFD16 0FFE16 Flash memory control register (FMCR) 0FFF16 Reserved area
Fig. 9 Memory map of special function register (SFR)
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS Direction Registers
The I/O ports P0-P6 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit of the direction register, the corresponding pin becomes an input pin. As for ports P0-P2, when "1" is written to the bit of the direction register and the segment output disable register, the corresponding pin becomes an output pin. As for ports P3-P6, when "1" is written to the bit of the direction register, the corresponding pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
b7
b0 PULL register (PULL : address 0FF116) P30-P33 pull-up P34-P37 pull-up P40-P43 pull-up P44-P47 pull-up P50-P53 pull-up P54-P57 pull-up P60-P62 pull-up Not used (return "0" when read) 0: No pull-up 1: Pull-up
b7
b0
Segment output disable register 0 (SEG0 : address 0FF816) P00 pull-up P01 pull-up P02 pull-up P03 pull-up P04 pull-up P05 pull-up P06 pull-up P07 pull-up
Pull-up Control
Each individual bit of ports P0-P2 can be pulled up with a program by setting direction registers and segment output disable registers 0 to 2 (addresses 0FF816 to 0FFA16). The pin is pulled up by setting "0" to the direction register and "1" to the segment output disable register. By setting the PULL register (address 0FF116), ports P3-P6 can control pull-up with a program. However, the contents of PULL register do not affect ports programmed as the output ports.
b7 b0
Segment output disable register 1 (SEG1 : address 0FF916) P10 pull-up P11 pull-up P12 pull-up P13 pull-up P14 pull-up P15 pull-up P16 pull-up P17 pull-up b7 b0 Segment output disable register 2 (SEG2 : address 0FFA16)
Segment output disable register Direction register
P20 pull-up
"0" Input port No pull-up Segment output
"1" Input port Pull-up Port output
Initial state
P21 pull-up P22 pull-up P23 pull-up P24 pull-up P25 pull-up P26 pull-up P27 pull-up 0: No pull-up 1: Pull-up
"0"
"1"
Note: The PULL register and segment output disable register affect only ports programmed as the input ports.
Fig. 10 Structure of ports P0 to P2 Fig. 11 Structure of PULL register and segment output disable register
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 List of I/O port function Pin P00/SEG0 - P03/SEG3 P04/SEG4 - P07/SEG7 P10/SEG8 - P17/SEG15 P20/SEG16 - P25/SEG21 P26/SEG22/VL1 P27/SEG23/VL2 P30/SRDY2 P31/SCLK2 P32/TxD2 P33/RxD2 P34/INT2 Name Port P0 Input/Output Input/Output, individual bits I/O format Non-port function Related SFRs CMOS compatible LCD segment Key input Segment output disable input level output (key-on wakeup) register 1 CMOS 3-state output interrupt input Ref. No. (1)
(2) Port P1 Input/Output, individual bits Input/Output, individual bits CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output Segment output disable register 2 Segment output disable register 3 LCD power input Serial I/O2 function I/O
Port P2
Port P3
Input/Output, individual bits
External interrupt input
P35/TXOUT P36/T2OUT/ P37/CNTR0 P40/OOUT0/AN0 P41/OOUT1/AN1 P42/AN2- P45/AN5 P46/RTP0/AN6 P47/RTP1/AN7 P50/INT0 P51/INT1 P52/T3OUT/PWM0 P53/T4OUT/PWM1 P54/RxD1 P55/TxD1 P56/SCLK1 P57/SRDY1 P60/CNTR1 P61/XCIN P62/XCOUT COM0-COM3 Port P5 Input/Output, individual bits CMOS compatible input level CMOS 3-state output Port P4 Input/Output, individual bits
Timer X output Timer 2 output Timer X function input CMOS compatible A-D conversion Oscillation input level input external CMOS 3-state output output
PULL register Serial I/O2 control register Serial I/O2 status register UART2 control register PULL register Interrupt edge selection register PULL register Timer X mode register Timer 12 mode register PULL register Timer X mode register PULL register A-D control register
(3) (4) (5) (6) (7)
(8) (9) (7) (11)
(10) Real time port function output External interrupt input PULL register A-D control register Timer Y mode register PULL register Interrupt edge selection register PULL register Timer 12 mode register (11)
(7)
Port P6
Input/Output, individual bits
Common
Output
Timer 3 output Timer 4 output PWM output Serial I/O1 Key input PULL register (key-on wakeup) Serial I/O1 control register function I/O interrupt input Serial I/O1 status register UART1 control register CMOS compatible Timer Y function input PULL register input level Timer Y mode register CMOS 3-state output Sub-clock oscillation circuit PULL register CPU mode register LCD common output LCD mode register
(9)
(12) (13) (14) (15) (7) (16) (17) (18)
Notes 1: For details of how to use double/triple function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Ports P04-P07, P1, P2 (1) Ports P00-P03
VL2/VL3 Segment output disable bit Segment data VL1/VSS Segment output disable bit Segment output disable bit Segment output disable bit Segment data VL1/VSS VL2/VL3
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Key-on wakeup interrupt input
Key input control
LCD power input (VL1,VL2) only for P26,P27
(3) Port P30
(4) Port P31
Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register
Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register
Pull-up control
Pull-up control
Data bus
Port latch
Data bus
Port latch
Serial I/O ready output
Serial I/O clock output Serial I/O clock input
(5) Port P32
P32/TxD2 P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register Pull-up control
(6) Port P33
Serial I/O enable bit Receive enable bit Direction register Pull-up control
Data bus
Port latch
Data bus
Port latch
Serial I/O output
Serial I/O input
Fig. 12 Port block diagram (1)
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7) Ports P34, P37, P50, P51, P60
Pull-up control
(8) Port P35
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
CNTR0, CNTR1 interrupt input INT0-INT2 interrupt input
Pulse output mode Timer X output
(9) Ports P36, P52, P53
Pull-up control
(10) Ports P42-P45
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Port/Timer output selection Timer output/PWM output Timer output/System clock output
A-D conversion input Analog input pin selection bit
(11) Ports P40, P41, P46, P47
(12) Port P54
Pull-up control Serial I/O enable bit Receive enable bit Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillation output control bit/ Real time control bit Oscillation output/ Data for real time port A-D conversion input Analog input pin selection bit
Serial I/O input Key-on wakeup interrupt input Key input control
(14) Port P56 (13) Port P55
P55/TxD1 P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register Pull-up control Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Pull-up control
Data bus
Port latch
Data bus
Port latch
Serial I/O output
Serial I/O clock output Serial I/O clock input
Key-on wakeup interrupt input
Key input control
Key-on wakeup interrupt input
Key input control
Fig. 13 Port block diagram (2)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(15) Port P57
Pull-up control
(16) Port P61
Xc oscillation enabled + Pull-up control Xc oscillation enabled Direction register
Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O ready output
Sub-clock generation circuit input
Key-on wakeup interrupt input
Key input control
(17) Port P62
Xc oscillation enabled + Pull-up control Xc oscillation enabled Direction register
(17) COM0-COM3
VL3
VL2 Data bus Port latch VL1
Gate input signal of each gate depends on the duty ratio and bias values.
VSS
Oscillator Port P61 Xc oscillation enabled
Fig. 14 Port block diagram (3)
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by nineteen sources: six external, twelve internal, and one software.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. The interrupt jump destination address is read from the vector table into the program counter.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first.
s Notes on Interrupts
When the active edge of an external interrupt (INT0 - INT2, CNTR0 or CNTR1) is set or an interrupt source where several interrupt source is assigned to the same vector address is switched, the corresponding interrupt request bit may also be set. Therefore, take following sequence: (1) Disable the interrupt. (2) Set the interrupt edge selection register (Timer X control register for CNTR0, Timer Y mode register for CNTR1). (3) Clear the set interrupt request bit to "0." (4) Enable the interrupt.
Table 7 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 INT2 Key input (key-on wakeup) Serial I/O1 receive Serial I/O1 transmit Serial I/O2 receive Serial I/O2 transmit Timer X Timer 1 Timer 2 Timer 3 Timer 4 CNTR0 Timer Y CNTR1 A-D conversion BRK instruction Priority 1 2 3 4 Vector Addresses (Note 1) Interrupt Request Generating Conditions High Low At reset FFFD16 FFFC16 At detection of either rising or falling FFFB16 FFFA16 edge of INT0 input At detection of either rising or falling FFF916 FFF816 edge of INT1 input At detection of either rising or falling FFF716 FFF616 edge of INT2 input At falling of ports P00-P03, P54-P57 input logical level AND At completion of serial I/O1 data receive FFF516 FFF416 At completion of serial I/O1 transmit FFF316 FFF216 shift or transmit buffer is empty At completion of serial I/O2 data receive FFF116 FFF016 At completion of serial I/O2 transmit FFEF16 FFEE16 shift or transmit buffer is empty At timer X underflow FFED16 FFEC16 At timer 1 underflow FFEB16 FFEA16 At timer 2 underflow FFE916 FFE816 At timer 3 underflow FFE716 FFE616 At timer 4 underflow FFE516 FFE416 At detection of either rising or falling FFE316 FFE216 edge of CNTR0 input At timer Y underflow FFE116 FFE016 At detection of either rising or falling edge of CNTR1 input At completion of A-D conversion FFDF16 FFDE16 FFDD16 FFDC16 At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when INT2 interrupt is selected External interrupt (active edge selectable) Valid when key input interrupt is selected External interrupt (falling valid) Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected Valid only when serial I/O2 is selected Valid only when serial I/O2 is selected
5 6 7 8 9 10 11 12 13 14 15
Valid only when timer 1 interrupt is selected Valid only when timer 2 interrupt is selected
External interrupt (active edge selectable)
External interrupt (active edge selectable) Valid when A-D conversion interrupt is selected Non-maskable software interrupt
16 17
Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 15 Interrupt control
b7
b0
Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT2/Key input interrupt switch bit Timer Y/CNTR1 interrupt switch bit Not used (return "0" when read) (Do not write to "1") 0 : Falling edge active 1 : Rising edge active 0 : INT2 interrupt 1 : Key input interrupt 0 : Timer Y interrupt 1 : CNTR1 interrupt
b7
b0
Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit INT2 interrupt request bit Key input interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit Timer X interrupt request bit
b7
b0
Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CNTR0 interrupt request bit Timer Y interrupt request bit CNTR1 interrupt request bit AD conversion interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0
Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit INT2 interrupt enable bit Key input interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit Timer X interrupt enable bit
b7
b0
Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CNTR0 interrupt enable bit Timer Y interrupt enable bit CNTR1 interrupt enable bit AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write to "1".) 0 : Interrupts disabled 1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by detecting the falling edge from any pin of ports P00-P03, P54-P57 that have been set to input mode. In other words, it is generated when AND of input level
goes from "1" to "0". An example of using a key input interrupt is shown in Figure 17, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P54-P57.
Port PXx "L" level output Segment output disable register 1 Bit 3 = "1"

Port P03 direction register = "1" Key input control register = "1" Port P03 latch
Key input interrupt request
P03 output Segment output Port P02 disable register 1 direction register = "1" Bit 2 = "1" Key input control register = "1" Port P02 latch
P02 output Segment output disable register 1 Bit 1 = "1"

Port P01 direction register = "1" Key input control register = "1" Port P01 latch
Port P0 Input reading circuit
P01 output Segment output Port P00 disable register 1 direction register = "1" Bit 0 = "1" Key input control register = "1" Port P00 latch
P00 output Port P57 direction register = "0" Key input control register = "1" Port P57 latch
P57 input
P56 input
Port P56 direction register = "0" Key input control register = "1" Port P56 latch
P55 input
Port P55 direction register = "0" Key input control register = "1" Port P55 latch
Port P5 Input reading circuit
P54 input
Port P54 direction register = "0" Key input control register = "1" Port P54 latch
PULL register Bit 5 = "1" P-channel transistor for pull-up CMOS output buffer
Fig. 17 Connection example when using key input interrupt and ports P0 and P5 block diagram
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A key input interrupt is controlled by the key input control register and port direction registers. When the key input interrupt is enabled, set "1" to the key input control register. A key input of any pin of ports P00-P03, P54-P57 that have been set to input mode is accepted.
b7
b0
Key input control register (KIC : address 0FF216) P54 key input control bit P55 key input control bit P56 key input control bit P57 key input control bit P00 key input control bit P01 key input control bit P02 key input control bit P03 key input control bit 0 : Key input interrupt disabled 1 : Key input interrupt enabled
Fig. 18 Structure of key input control register
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS 8-Bit Timer
The 38C2 group has four built-in timers : Timer 1, Timer 2, Timer 3, and Timer 4. Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches "0016," the contents of the timer latch is reloaded into the timer with the next count pulse. In this mode, the interrupt request bit corresponding to that timer is set to "1." The count can be stopped by setting the stop bit of each timer to "1."
q Frequency Divider For Timer
Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for the count source. The count source of the frequency divider is switched to XIN or XCIN by the CPU mode register. The frequency divider is controlled by the 3-bit register. The division ratio can be selected from as follows; 1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN) or f(XCIN).
qTimer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. Also, by the timer 12 mode register, each time timer 2 underflows, the signal of which polarity is inverted can be output from P36/T2OUT pin. At reset, all bits of the timer 12 mode register are cleared to "0," timer 1 is set to "FF16," and timer 2 is set to "0116." When executing the STP instruction, previously set the wait time at return.
q Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. Also, by the timer 34 mode register, each time timer 3 or timer 4 underflows, the signal of which polarity is inverted can be output from P52/T3OUT pin or P53/T4OUT pin.
q Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
A PWM rectangular waveform corresponding to the 10-bit accuracy can be output from the P52/PWM0 pin and P53/PWM1 pin by setting the timer 34 mode register and PWM01 register (refer to Figure 21). The "n" is the value set in the timer 3 (address 002216) or the timer 4 (address 002316). The "ts" is one period of timer 3 or timer 4 count source. One output pulse is the short interval. Four output pulses are the long interval. "H" width of the short interval is obtained by n ts. However, in the long interval, "H" width of output pulse is extended for ts which is set by the PWM01 register (address 002416).
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Timer 12 mode register (T12M: address 002516) Timer 1 count stop bit 0 : Count operation 1 : Count stop Timer 2 count stop bit 0 : Count operation 1 : Count stop Timer 1 count source selection bits b3 b2 0 0 : Frequency divider for Timer 1 0 1 : f(XCIN) 1 0 : Underflow of Timer Y 1 1 : Not available Timer 2 count source selection bits b5 b4 0 0 : Underflow of Timer 1 0 1 : f(XCIN) 1 0 : Frequency divider for Timer 2 1 1 : Not available Timer 2 output selection bit (P36) 0 : I/O port 1 : Timer 2 output T2OUT output edge switch bit 0 : Start at "L" output 1 : Start at "H" output
PWM01 register (PWM01: address 002416) PWM0 set bits b1 b0 0 0 : No extended 0 1 : Extended once in four periods 1 0 : Extended twice in four periods 1 1 : Extended three times in four periods PWM1 set bits b3 b2 0 0 : No extended 0 1 : Extended once in four periods 1 0 : Extended twice in four periods 1 1 : Extended three times in four periods Not used (returns "0" when read)
b7
b0
b7
b0
Timer 34 mode register (T34M: address 002616) Timer 3 count stop bit 0 : Count operation 1 : Count stop Timer 4 count stop bit 0 : Count operation 1 : Count stop Timer 3 count source selection bit 0 : Frequency divider for Timer 3 1 : Underflow of Timer 2 Timer 4 count source selection bits b4 b3 0 0 : Frequency divider for Timer 4 0 1 : Underflow of Timer 3 1 0 : Underflow of Timer 2 1 1 : Not available Timer 3 operating mode selection bit 0 : Timer mode 1 : PWM mode Timer 4 operating mode selection bit 0 : Timer mode 1 : PWM mode Not used (returns "0" when read)
b7 b0
Timer 12 frequency division selection register (PRE12: address 0FF516) Timer 1 frequency division selection bits b2 b1 b0 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Timer 2 frequency division selection bits b5 b4 b3 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Not used (returns "0" when read)
Timer 1234 mode register (T1234M: address 0FF316) T3OUT output edge switch bit 0 : Start at "L" output 1 : Start at "H" output T4OUT output edge switch bit 0 : Start at "L" output 1 : Start at "H" output Timer 3 output selection bit (P52) 0 : I/O port 1 : Timer 3 output Timer 4 output selection bit (P53) 0 : I/O port 1 : Timer 4 output Timer 2 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 3 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 4 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Not used (returns "0" when read)
b7 b0
Timer 34 frequency division selection register (PRE34: address 0FF616) Timer 3 frequency division selection bits b2 b1 b0 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Timer 4 frequency division selection bits b5 b4 b3 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Not used (returns "0" when read)
Fig. 19 Structure of timer related register
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN System clock control bits Frequency divider 12
Clock for Timer 1 Clock for Timer 2 Clock for Timer 3 Clock for Timer 4
Timer 1 Timer 2 Timer 3 Timer 4
Frequency division selection bits (3 bits for each Timer)
Data bus
XCIN
XCIN Clock for Timer 1 Timer Y output
Timer 1 count "00" source selection bits "01" "10" Timer 1 count stop bit
Timer 1 latch (8)
Timer 1 interrupt request
Timer 1 (8)
The following values can be selected the clock for Timer; 1/1,1/2,1/16,1/32, 1/64,1/128,1/256,1/1024
Timer 2 count "00" source selection bits
Timer 2 write control bit
Timer 2 latch (8)
Timer 2 interrupt request
P36/T2OUT/f/(LED6)
P36 clock output control bit System clock f "1" "0" "0"
Clock for Timer 2
"01"
"10" Timer 2 output control bit Timer 2 count stop bit
Timer 2 (8)
P36 direction register
P36 latch
S 1/2 Q T "1" Q T2OUT output edge switch bit Timer 3 write control bit Timer 3 count source "1" selection bit
Timer 2 output selection bit
Timer 3 latch (8)
Timer 3 interrupt request
Clock for Timer 3
10 bit PWM0 circuit Timer 3 output control bit "0" S Q P52 P52 direction T "1" latch register Q 1/2 T3OUT output Timer 3 output selection bit edge switch bit "0"
Timer 3 (8)
"0"
Timer 3 count stop bit
P52/PWM0/T3OUT
Timer 3 operating mode selection bit "1"
PWM01 register (2)
Timer 4 write control bit "01" Timer 4 count source "10" selection bits
Timer 4 latch (8)
Timer 4 interrupt request
Clock for Timer 4
Timer 4 operating mode selection bit 10 bit PWM1 circuit Timer 4 output control bit "0" P53 direction register P53 T "1" latch 1/2 Q T4OUT output Timer 4 output selection bit edge switch bit "0" S Q
Timer 4 (8)
"00"
Timer 4 count stop bit
P53/PWM1/T4OUT
"1"
PWM01 register (2)
Fig. 20 Block diagram of timers 1, 2, 3 and 4
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Output waveform of Timer 3 PWM0 or Timer 4 PWM1
Long interval 4 256 ts Short interval 256 ts PWM01 register = "002"
n ts
Short interval 256 ts
n ts
Short interval 256 ts
n ts
Short interval 256 ts
n ts
PWM01 register = "012"
(n+1) ts
n ts
n ts
n ts
PWM01 register = "102"
(n+1) ts
n ts
(n+1) ts
n ts
PWM01 register = "112"
(n+1) ts
(n+1) ts
(n+1) ts
n ts
n: Setting value of Timer 3 or Timer 4 ts: One period of Timer 3 count source or Timer 4 count source PWM01 register (address 002416) : 2-bit value corresponding to PWM0 or PWM1
Fig. 21 Waveform of PWM01
16-bit Timer q Frequency Divider For Timer
Each timer X and timer Y have the frequency dividers for the count source. The count source of the frequency divider is switched to XIN or XCIN by the CPU mode register. The division ratio of each timer can be controlled by the 3-bit register. The division ratio can be selected from as follows; 1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN) or f(XCIN).
(3) IGBT Output Mode
After dummy output from the TXOUT pin, count starts with the INT0 pin input as a trigger. In the case that the timer X output edge switch bit is "0", when the trigger is detected or the timer X underflows, "H" is output from the TXOUT pin. When the count value corresponds with the compare register value, the TXOUT output becomes "L". After noise is cleared by noise filters, judging continuous 4-time same levels with sampling clocks to be signals, the INT0 signal can use 4 types of delay time by a delay circuit. When using this mode, set the port sharing the INT0 pin to input mode and set the port sharing the TXOUT pin to output mode. When the timer X output control bit 1 or 2 of the timer X control register is set to "1", the timer X count stop bit is fixed to "1" forcibly by the interrupt signal of INT1 or INT2. And then, by stopping the timer X counting, the TXOUT output can be fixed to the signal output at that time. Do not write "1" to the timer X register (extension) when using the IGBT output mode.
q Timer X
The timer X count source can be selected by setting the timer X mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. The timer X operates as down-count. When the timer contents reach "000016", an underflow occurs at the next count pulse and the timer latch contents are reloaded. After that, the timer continues countdown. When the timer underflows, the interrupt request bit corresponding to the timer X is set to "1". Six operating modes can be selected for timer X by the timer X mode register and timer X control register.
(4) PWM Mode
IGBT dummy output, an external trigger with the INT0 pin and output control with pins INT1 and INT2 are not used. Except for those, this mode operates just as in the IGBT output mode. The period of PWM waveform is specified by the timer X set value. In the case that the timer X output edge switch bit is "0", the "H" interval is specified by the compare register set value. When using this mode, set the port sharing the TXOUT pin to output mode. Do not write "1" to the timer X register (extension) when using the PWM mode.
(1) Timer Mode
The count source can be selected by setting the timer X mode register. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension).
(2) Pulse Output Mode
Pulses of which polarity is inverted each time the timer underflows are output from the TXOUT pin. Except for that, this mode operates just as in the timer mode. When using this mode, set the port sharing the TXOUT pin to output mode.
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts Timer X count source
Timer X PWM mode IGBT mode
(n-m+1) ts (n+1) ts
m ts
When the Timer X setting value = n and the compare register setting value = m, the following PWM waveform is output; Duty : (n-m+1)/(n+1) Period : (n+1) ts (ts: period of timer X count source)
Fig. 22 Waveform of PWM/IGBT
(5) Event Counter Mode
The timer counts signals input through the CNTR0 pin. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). When using this mode, set the port sharing the CNTR0 pin to input mode. In this mode, the window control can be performed by the timer 1 underflow. When the bit 5 (data for control of event counter window) of the timer X mode register is set to "1", counting is stopped at the next timer 1 underflow. When the bit is set to "0", counting is restarted at the next timer 1 underflow.
* In the IGBT and PWM modes, do not write "1" to the timer X register (extension). Also, when "1" is already written to the timer X register, be sure to write "0" to the register before using. Write to the following registers in the order as shown below; the compare register (high- and low-order), the timer X register (extension), the timer X register (low-order), the timer X register (high-order). It is possible to use whichever order to write to the compare register (high- and low-order). However, write both the compare register and the timer X register at the same time.
(6) Pulse Width Measurement Mode
In this mode, the count source is the output of frequency divider for timer. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). When the bit 6 of the CNTR0 active edge switch bits is "0", counting is executed during the "H" interval of CNTR0 pin input. When the bit is "1", counting is executed during the "L" interval of CNTR0 pin input. When using this mode, set the port sharing the CNTR0 pin to input mode.
(2) Read Order to Timer X
* In all modes, read the following registers in the order as shown below; the timer X register (extension), the timer X register (high-order), the timer X register (low-order). When reading the timer X register (extension) is not required, read the timer X register (high-order) first and the timer X register (loworder). Read order to the compare register is not specified. * If reading to the timer X register during write operation or writing to it during read operation is performed, normal operation will not be performed.
s Notes on Timer X (1) Write Order to Timer X
* In the timer mode, pulse output mode, event counter mode and pulse width measurement mode, write to the following registers in the order as shown below; the timer X register (extension), the timer X register (low-order), the timer X register (high-order). Do not write to only one of them. When the above mode is set and timer X operates as the 16-bit counter, if the timer X register (extension) is never set after reset is released, setting the timer X register (extension) is not required. In this case, write the timer X register (low-order) first and the timer X register (high-order). However, once writing to the timer X register is executed, note that the value is retained to the reload latch.
(3) Write to Timer X
* When writing a value to the timer X address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. Normally, when writing a value to the timer X address, the value is set into the timer and the timer latch at the same time, because they are written at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch. * Do not switch the timer count source during timer count operation. Stop the timer count before switching it.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(4) Set of Timer X Mode Register
Set the write control bit of the timer X mode register to "1" (write to the latch only) when setting the IGBT output and PWM modes. Output waveform simultaneously reflects the contents of both registers at the next underflow after writing to the timer X register (highorder).
s Notes on Timer Y q CNTR1 Interrupt Active Edge Selection
CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit.
(5) Output Control Function of Timer X
When using the output control function (INT1 and INT2) in the IGBT output mode, set the levels of INT1 and INT2 to "H" in the falling edge active or to "L" in the rising edge active before switching to the IGBT output mode.
q Timer Y Read/Write Control
* When reading from/writing to timer Y, read from/write to both the high-order and low-order bytes of timer Y. When the value is read, read the high-order bytes first and the low-order bytes next. When the value is written, write the low-order bytes first and the highorder bytes next. If reading from the timer Y register during write operation or writing to it during read operation is performed, normal operation will not be performed. * When writing a value to the timer Y address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. Normally, when writing a value to the timer Y address, the value is set into the timer and the timer latch at the same time, because they are set to write at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch. * Do not switch the timer count source during timer count operation. Stop the timer count before switching it.
(6) Note on Switch of CNTR0 Active Edge
* When the CNTR0 active edge switch bits are set, at the same time, the interrupt active edge is also affected. * When the pulse width is measured, set the bit 7 of the CNTR0 active edge switch bits to "0".
Timer Y
Timer Y is a 16-bit timer. The timer Y count source can be selected by setting the timer Y mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. Four operating modes can be selected for timer Y by the timer Y mode register. Also, the real time port can be controlled.
(1) Timer Mode
The timer Y count source can be selected by setting the timer Y mode register.
q Real Time Port Control
When the real time port function is valid, data for the real time port is output from ports P47 and P46 each time the timer Y underflows. (However, if the real time port control bit is changed from "0" to "1" after the data for real time port is set, data is output independent of the timer Y operation.) When the data for the real time port is changed while the real time port function is valid, the changed data is output at the next underflow of timer Y. Before using this function, set the corresponding port direction registers to output mode.
(2) Period Measurement Mode
The interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting. Except for that, this mode operates just as in the timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 pin input is found by CNTR1 interrupt. When using this mode, set the port sharing the CNTR1 pin to input mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin. Except for that, this mode operates just as in the timer mode. When using this mode, set the port sharing the CNTR1 pin to input mode.
(4) Pulse Width HL Continuously Measurement Mode
The interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for that, this mode operates just as in the period measurement mode. When using this mode, set the port sharing the CNTR1 pin to input mode.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Timer X mode register (TXM: address 002F16) Timer X operating mode bits b2 b1 b0 0 0 0 : Timer mode 0 0 1 : Pulse output mode 0 1 0 : IGBT output mode 0 1 1 : PWM mode 1 0 0 : Event counter mode 1 0 1 : Pulse width measurement mode Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer X count source selection bit 0 : Frequency divider output 1 : f(XCIN) Data for control of event counter window 0 : Event count enabled 1 : Event count disabled Timer X count stop bit 0 : Count operation 1 : Count stop Timer X output selection bit (P35) 0 : I/O port 1 : Timer X output
Timer X control register (TXCON: address 0FF416) Noise filter sampling clock selection bit 0 : f(XIN)/2 1 : f(XIN)/4 External trigger delay time selection bits b2 b1 0 0 : Not delayed 0 1 : (4/f(XIN)) s 1 0 : (8/f(XIN)) s 1 1 : (16/f(XIN)) s Timer X output control bit 1 (P51) 0 : Not used 1 : INT1 interrupt used Timer X output control bit 2 (P34) 0 : Not used 1 : INT2 interrupt used Timer X output edge switch bit 0 : Start at "L" output 1 : Start at "H" output CNTR0 active edge switch bits b7 b6 0 0 : Count at rising edge in event counter mode Falling edge active for CNTR0 interrupt Measure "H" pulse width in pulse width measurement mode 0 1 : Count at falling edge in event counter mode Rising edge active for CNTR0 interrupt Measure "L" pulse width in pulse width measurement mode 1 0 : Count at both edges in event counter mode Both edges active for CNTR0 interrupt 1 1 : Count at both edges in event counter mode Both edges active for CNTR0 interrupt
b7
b0
Timer Y mode register (TYM: address 003016) Real time port control bit 0 : Real time port function invalid 1 : Real time port functin valid P46 data for real time port P47 data for real time port Timer Y count source selection bit 0 : Frequency divider output 1 : f(XCIN) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuous measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure falling period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure rising period in period measurement mode Rising edge active for CNTR1 interrupt Timer Y count stop bit 0 : Count operation 1 : Count stop
b7
b0
Timer XY frequency division selection register (PREXY: address 0FF716) Timer X frequency division selection bits b2 b1 b0 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Timer Y frequency division selection bits b5 b4 b3 0 0 0 : 1/16 f(XIN) or 1/16 f(XCIN) 0 0 1 : 1/1 f(XIN) or 1/1 f(XCIN) 0 1 0 : 1/2 f(XIN) or 1/2 f(XCIN) 0 1 1 : 1/32 f(XIN) or 1/32 f(XCIN) 1 0 0 : 1/64 f(XIN) or 1/64 f(XCIN) 1 0 1 : 1/128 f(XIN) or 1/128 f(XCIN) 1 1 0 : 1/256 f(XIN) or 1/256 f(XCIN) 1 1 1 : 1/1024 f(XIN) or 1/1024 f(XCIN) Not used (returns "0" when read)
b7
b0
Timer Y mode register 2 (TYM2: address 0FFB16) Timer Y write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Not used (returns "0" when read)
Fig. 23 Structure of Timer X, Y related registers
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN XIN
System clock control bits 3 Timer X frequency division selection bit Timer Y frequency division selection bit
Data bus
Frequency divider
Frequency divider
3
1/2 "0 "
1/4 "1"
Noise filter sampling clock selection bit
XcIN
Delay time selection bits "00"
INT0 interrupt request
0 s
Timer X operating mode bits "010"
P50/INT0 Clock for Timer Y
The following values can be selected the clock for Timer; 1/1,1/2,1/16,1/32, 1/64,1/128,1/256,1/1024
Noise filter (4 times same levels judgment)
Delay circuit
4/f(XIN) "01" 8/f(XIN) "10" 16/f(XIN)"11"
Clock for Timer X
"0"
Count source selection bit
"000" "001" "011" "100" "101"
XcIN
"1"
Data for control of event counter window Timer 1 interrupt
DQ Latch
"00"
P37/CNTR0/(LED7)
"01"
Timer X operating Timer X write mode bits control bit "000" "001" Timer X count "010" stop bit "011" Timer X (low-order) latch (8) Timer X (high-order) latch (8) "101"
Extend latch (2)
Timer X (low-order)(8)
"100"
Timer X (high-order)(8) Extend counter (2)
Timer X interrupt request CNTR0 interrupt request
Both edges detection
"10" "11" CNTR0 active edge switch bits
Pulse width measurement mode
Equal
TXOUT output control bit 1 Timer X operating mode bits "010" Edge detection TXOUT output control bit 2 Compare register (low-order)(8) Compare register (high-order)(8)
P51/INT1
R S Q Q "0"
Pulse output mode
P34/INT2/(LED4)
T
P35/TXOUT/(LED5) "1 "
P35 direction register P35 latch TXOUT edge switch bit IGBT output mode PWM mode
S S Q Q
Timer Y operating mode bits
T
Output selection bit
"00", "01", "10" Clock for Timer Y XcIN
"1" Count source selection bit "0" Pulse width HL continuous measurement mode
CNTR1 interrupt request "11"
Rising edge detection Falling edge detection
Timer Y write control bit Timer Y count stop bit CNTR1 active edge switch bit
Period measurement mode
"0 " P60/CNTR1 "1 "
Real time port control bit
"00", "01", "11"
Timer Y operating mode bits
Timer Y (low-order) latch (8) Timer Y (high-order) latch (8)
Timer Y (low-order)(8) "10"
Timer Y (high-order)(8)
Timer Y interrupt request
"1 "
Real time port control bit
QD Latch
P47 data for real time port
"0"
P47/RTP1/AN7
P47 direction register
Timer Y mode register write signal
"0"
P47 latch
"1"
Real time port control bit "1"
QD Latch
P46 data for real time port
P46/RTP0/AN6
P46 direction register
"0"
P46 latch
Fig. 24 Block diagram of Timer X, Y
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
The 38C2 group has built-in two 8-bit serial I/O. Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
Data bus Address 001C16 [Address 001E16] Receive buffer register P54/RXD1 [P33/RXD2] Receive shift register Shift clock P56/SCLK1 [P31/SCLK2] Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 0FE216 [Address 0FE516] 1/4 Serial I/O control register Address 0FE016 [Address 0FE316] Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P57/SRDY1 [P30/SRDY2] P55/TXD1 [P32/TXD2] F/F Falling-edge detector
Clock control circuit Shift clock Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001D16 [Address 001F16]
Transmit shift register Transmit buffer register Address 001C16 [Address 001E16] Data bus
[ ] : For Serial I/O2
Fig. 25 Block diagram of clock synchronous serial I/O
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY Write pulse to receive/transmit buffer register TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 26 Operation of clock synchronous serial I/O function
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Data bus Address 001C16 [Address 001E16]
Receive buffer register OE Character length selection bit ST detector 7 bits Receive shift register
Serial I/O control register
Address 0FE016 [Address 0FE316] Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16
P54/RXD1 [P33/RXD2]
8 bits PE FE SP detector Clock control circuit Serial I/O synchronous clock selection bit P56/SCLK1 [P31/SCLK2] BRG count source selection bit Frequency division ratio 1/(n+1) f(XIN) Baud rate generator (f(XCIN) in low-speed mode) Address 0FE216 [Address 0FE516] 1/4 ST/SP/PA generator 1/16 P55/TXD1 [P32/TXD2] Character length selection bit Transmit buffer register Address 001C16 [Address 001E16] Data bus Transmit shift register
UART control register Address 0FE116 [Address 0FE416]
Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001D16 [Address 001F16]
[ ] : For Serial I/O2
Fig. 27 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1
Serial output TXD
ST
D0
D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
SP
ST
D0
D1
SP Generated at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=0 RBF=1 RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 28 Operation of UART serial I/O function
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer Register/Receive Buffer Register (TB/RB)]
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0".
[Serial I/O Status Register (SIO1STS, SIO2STS)]
The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".
[Serial I/O Control Register (SIO1CON, SIO2CON)]
The serial I/O control register consists of eight control bits for the serial I/O function.
[UART Control Register (UART1CON, UART2CON)]
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P55/TXD1 [P32/TxD2] pin.
[Baud Rate Generator (BRG1, BRG2)]
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O status register (SIO1STS : address 001D 16) [SIO2STS : address 001F 16] Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O control register (SIO1CON : address 0FE0 16) [SIO2CON : address 0FE3 16] BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P57 [P30] pin operates as ordinary I/O pin 1: P57 [P30] pin operates as S RDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P54 [P30] to P57 [P33] operate as ordinary I/O pins) 1: Serial I/O enabled (pins P54 [P30] to P57 [P33] operate as serial I/O pins)
b7
b0
UART control register (UART1CON : address 0FE1 16) [UART2CON : address 0FE4 16] Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P55/TXD1 [P32/TxD2] P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read)
( ) : For Serial I/O1 [ ] : For Serial I/O2
Fig. 29 Structure of serial I/O related registers
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The 38C2 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion.
b7
b0 A-D control register (ADCON: address 001916)
[A-D Conversion Register (ADL, ADH)]
One of these registers is a high-order register, and the other is a loworder register. The high-order 8 bits of a conversion result is stored in the A-D conversion register (high-order) (address 001B16), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the A-D conversion register (low-order) (address 001A16). During A-D conversion, do not read these registers. Also, the connection between the resistor ladder and reference voltage input pin (VREF) can be controlled by the VREF input switch bit (bit 0 of address 001A16). When "1" is written to this bit, the resistor ladder is always connected to VREF. When "0" is written to this bit, the resistor ladder is disconnected from VREF except during the A-D conversion.
[A-D Control Register (ADCON)]
This register controls A-D converter. Bits 2 to 0 are analog input pin selection bits. Bit 3 is an AD conversion completion bit and "0" during AD conversion. This bit is set to "1" upon completion of A-D conversion. A-D conversion is started by setting "0" in this bit.
Analog input pin selection bits b2 b1 b0 0 0 0: P40/AN0 0 0 1: P41/AN1 0 1 0: P42/AN2 0 1 1: P43/AN3 1 0 0: P44/AN4 1 0 1: P45/AN5 1 1 0: P46/AN6 1 1 1: P47/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed AD conversion clock selection bits b5 b4 0 0: Frequency not divided 0 1: Frequency divided by 2 1 0: Frequency divided by 4 1 1: Frequency divided by 8 10-bit or 8-bit conversion switch bit 0: 10-bit AD 1: 8-bit AD Booster selection bit 0: Booster not used 1: Booster used
10-bit reading (Read address 001B16 before 001A16)
b7 b0
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS and VREF, and outputs the divided voltages.
A-D conversion register 1 b9 b8 b7 b6 b5 b4 b3 b2 (high-order) (Address 001B 16) A-D conversion register 2 b1 b0 (Address 001A 16)
* VREF input switch bit 0: ON only during A-D conversion 1: ON Note : The bit 5 to bit 1 of address 001A 16 becomes "0" at reading. Also, bit 0 is undefined at reading.
b7 b0
[Channel Selector]
The channel selector selects one of the input ports P47/AN7-P40/ AN0 and inputs it to the comparator.
*
(low-order)
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to "1."
8-bit reading (Read only address 001B16)
b7 b0
(Address 001B 16)
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 30 Structure of A-D control register
Data bus
b7 b0
A-D control register
3 P40/OOUT0/AN0 P41/OOUT1/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7
Channel selector
A-D control circuit
A-D interrupt request
Comparator
A-D conversion register (H)
A-D conversion register (L)
(Address 001B 16)
(Address 001A 16)
Resistor ladder
AVSS VREF
Fig. 31 Block diagram of A-D converter
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD DRIVE CONTROL CIRCUIT
The 38C2 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. * LCD display RAM * Segment output disable register * LCD mode register * Selector * Timing controller * Common driver * Segment driver * Bias control circuit A maximum of 24 segment output pins and 4 common output pins can be used. Up to 96 pixels can be controlled for an LCD display. When the LCD enable bit is set to "1" after data is set in the LCD mode register, the
segment output disable register, and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 8 Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixels 48 dots or 8 segment LCD 6 digits 72 dots or 8 segment LCD 9 digits 96 dots or 8 segment LCD 12 digits
b7
b0 LCD mode register (LM : address 003916) Duty ratio selection bits b1 b0 0 0 : Not used 0 1 : 2 (use COM0,COM1) 1 0 : 3 (use COM0-COM2) 1 1 : 4 (use COM0-COM3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON LCD drive timing selection bit 0 : Type A 1 : Type B LCD circuit divider division ratio selection bits b6 b5 0 0 : Clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note) 0 : f(XCIN)/32 1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
b7
b0 Segment output disable register 0 (SEG0 : address 0FF816) Segment output disable bit 0 0 : Segment output SEG0 1 : Output port P00 Segment output disable bit 1 0 : Segment output SEG1 1 : Output port P01 Segment output disable bit 2 0 : Segment output SEG2 1 : Output port P02 Segment output disable bit 3 0 : Segment output SEG3 1 : Output port P03 Segment output disable bit 4 0 : Segment output SEG4 1 : Output port P04 Segment output disable bit 5 0 : Segment output SEG5 1 : Output port P05 Segment output disable bit 6 0 : Segment output SEG6 1 : Output port P06 Segment output disable bit 7 0 : Segment output SEG7 1 : Output port P07
Note : LCDCK is a clock for an LCD timing controller.
b7
b0 Segment output disable register 1 (SEG1 : address 0FF916) Segment output disable bit 8 0 : Segment output SEG8 1 : Output port P10 Segment output disable bit 9 0 : Segment output SEG9 1 : Output port P11 Segment output disable bit 10 0 : Segment output SEG10 1 : Output port P12 Segment output disable bit 11 0 : Segment output SEG11 1 : Output port P13 Segment output disable bit 12 0 : Segment output SEG12 1 : Output port P14 Segment output disable bit 13 0 : Segment output SEG13 1 : Output port P15 Segment output disable bit 14 0 : Segment output SEG14 1 : Output port P16 Segment output disable bit 15 0 : Segment output SEG15 1 : Output port P17
b7
b0 Segment output disable register 2 (SEG2 : address 0FFA16) Segment output disable bit 16 0 : Output port P20 1 : Segment output SEG16 Segment output disable bit 17 0 : Output port P21 1 : Segment output SEG17 Segment output disable bit 18 0 : Output port P22 1 : Segment output SEG18 Segment output disable bit 19 0 : Output port P23 1 : Segment output SEG19 Segment output disable bit 20 0 : Output port P24 1 : Segment output SEG20 Segment output disable bit 21 0 : Output port P25 1 : Segment output SEG21 Segment output disable bit 22 0 : Output port P26 1 : Segment output SEG22 Segment output disable bit 23 0 : Output port P27 1 : Segment output SEG23
Note : Only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable register.
Fig. 32 Structure of LCD related registers
35
36
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Data bus
I
LCD enable bit Address 004C16 LCD display RAM LCDCK count source selection bit "0" LCD divider "1" f(XCIN)/32 f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) LCD circuit divider division ratio selection bits 2 Duty ratio selection bits
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Address 004016
Address 004116
Fig. 33 Block diagram of LCD controller/driver
2 Bias control bit LCD power control register Selector Selector 5 Timing controller LCDCK Level shift Level shift Bias control Level shift Level Level Level shift shift shift Segment Segment driver driver
Common Common Common Common driver driver driver driver
Selector Selector Selector Selector
Level shift
Level shift
Level shift
Level shift
Segment Segment Segment Segment driver driver driver driver
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C2 Group
P00/SEG0 P01/SEG1 P02/SEG2 P03/SEG3 P20/SEG16
P26/SEG22/VL1 P27/SEG23/VL2 VSS P26/ P27/ VL3 SEG22/ SEG23/ VL1 VL2
COM0 COM1 COM2 COM3
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bias Control and Applied Voltage to LCD Power Input Pins
When the voltage is applied from the LCD power input pins (VL1- VL3), set the VL pin input selection bit (bit 5 of the LCD power control register) and VL3 connection bit (bit 6 of LCD power control register) to "1", apply the voltage value shown in Table 9 according to the bias value. In this case, SEG22 pin and SEG23 pin cannot be used. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Table 9 Bias control and applied voltage to VL1-VL3 Bias value Voltage value VL3=VLCD 1/3 bias VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD 1/2 bias VL2=VL1=1/2 VLCD
Note : VLCD is the maximum value of supplied voltage for the LCD panel.
Common Pin and Duty Ratio Control
The common pins (COM0-COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). When reset is released, VCC voltage is output from the common pin. Table 10 Duty ratio control and common pins used Duty ratio 2 3 4 Duty ratio selection bit Bit 1 Bit 0 0 1 1 0 1 1 Common pins used COM0, COM1 COM0-COM2 COM0-COM3
Note: Unused common pin outputs the unselected waveform.
Segment Signal Output Pin
The segment signal output pins (SEG0-SEG23) are shared with ports P0-P2. When these pins are used as the segment signal output pins, set the direction registers of the corresponding pins to "1", and clear the segment output disable register to "0". Also, these pins are set to the input port after reset, the VCC voltage is output by the pull-up resistor.
Contrast adjust
Contrast adjust
VL3 R1 VL2
VL3 R4 VL2
R2 VL1 R3 VL1 R5
R1 = R2 = R3 1/3 bias 1/2 bias
R4 = R5
Fig. 34 Example of circuit at each bias (at external power input)
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Power Circuit
The LCD power circuit has the dividing resistor for LCD power which can be connected/disconnected with the LCD power control register.
b7
b0 LCD power control register (VLCON : address 003816) Dividing resistor for LCD power control bit (LCDRON) 0 : Internal dividing resistor disconnected from LCD power circuit 1 : Internal dividing resistor connected to LCD power circuit Dividing resistor for LCD power selection bits (RSEL) b3 b2 1 0 : Larger resistor 0 1: 0 0: 1 1 : Smaller resistor Not used (return "0" when read) (Do not write to "1") VL pin input selection bit (VLSEL) 0 : Input invalid 1 : VL input function valid VL3 connection bit 0 : Connect LCD internal VL3 to VCC 1 : Connect LCD internal VL3 to VL3 pin Not used (return "0" when read) (Do not write to "1")
Fig. 35 Structure of LCD power control register
LCD power control register (bit 6)
Vcc
VL3
LCD power control register (bit 5) LCD power control register (bit 0)
LCD internal VL3
P27/SEG23/ VL2
LCD internal VL2
P26/SEG22/ VL1
LCD internal VL1
LCD power control register (bits 2 and 1) Dividing resistor for LCD power
LCD mode register (bit 2)
Fig. 36 VL block diagram
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
The 12-byte area of address 004016 to 004B16 is the designated RAM for the LCD display. When "1" is written to these addresses, the corresponding segments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) duty ratio
LCD Drive Timing
For the LCD drive timing, type A or type B can be selected. The LCD drive timing is selected by the timing selection bit (bit 4 of LCD mode register). Type A is selected by setting the LCD drive timing selection bit to "0", type B is selected by setting the bit to "1". Type A is selected after reset.
f(LCDCK)=
Frame frequency=
s Note
(1) When the STP instruction is executed, the following bits are cleared to "0"; * LCD enable bit (bit 3 of LCD mode register) * Bits other than bit 6 of the LCD power control register. (2) When the voltage is applied to VL1 to VL3 by using the external resistor, write "102" to dividing resistor for LCD power selection bits (RSEL) of the LCD power control register (address 3816).
Bit Address
7
6
5
4
3
2
1
0
004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16
SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23
SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Fig. 37 LCD display RAM map
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal signal LCDCK timing
1/4 duty
Voltage level VL3 VL2=VL1 VSS
COM0 COM1 COM2 COM3 SEG0
VL3 VSS
LCD
OFF COM3 COM2 COM1
ON COM0 COM3
OFF COM2 COM1
ON COM0
1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2=VL1 VSS
SEG0
LCD
ON COM0
OFF COM2 COM1
ON COM0
OFF COM2 COM1
ON COM0
OFF COM2
1/2 duty COM0 COM1 SEG0 VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 VL3 VL2=VL1 VSS
LCD
Fig. 38 LCD drive waveform (1/2 bias, type A)
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal signal LCDCK timing
1/4 duty
Voltage level VL3 VL2 VL1 VSS
COM0
COM1 COM2 COM3 SEG0 VL3 VSS LCD OFF ON OFF ON
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
1/3 duty VL3 VL2 VL1 VSS
COM0 COM1 COM2
SEG0
VL3 VSS
LCD
ON
OFF
ON
OFF
ON
OFF
COM0 1/2 duty COM0 COM1 SEG0
COM2
COM1
COM0
COM2
COM1
COM0
COM2
VL3 VL2 VL1 VSS
VL3 VSS
LCD
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 39 LCD drive waveform (1/3 bias, type A)
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal signal LCDCK timing
1/4 duty
1 frame 1 frame
Voltage level VL3 VL2=VL1 VSS
COM0
COM1 COM2 COM3 SEG0 VL3 VSS LCD OFF ON OFF ON
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
1/3 duty
1 frame 1 frame
COM0 COM1 COM2
VL3 VL2=VL1 VSS
SEG0
VL3 VSS
LCD
ON
OFF
ON
OFF
ON
OFF
COM0 1/2 duty
1 frame
COM2
COM1
1 frame
COM0
COM2
1 frame
COM1
COM0
1 frame
COM2
COM0 COM1 SEG0
VL3 VL2=VL1 VSS
VL3 VSS
LCD
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 40 LCD drive waveform (1/2 bias, type B)
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal signal LCDCK timing
1/4 duty
1 frame 1 frame
Voltage level VL3 VL2 VL1 VSS
COM0
COM1 COM2 COM3 SEG0 VL3 VL2 VL1 VSS OFF ON OFF ON
LCD
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
1/3 duty
1 frame 1 frame
COM0 COM1 COM2
VL3 VL2 VL1 VSS
SEG0
VL3 VL2 VL1 VSS ON COM0 OFF COM2 COM1
1 frame
LCD
ON COM0
OFF COM2
1 frame
ON COM1 COM0
1 frame
OFF COM2
1/2 duty
1 frame
COM0 COM1 SEG0
VL3 VL2 VL1 VSS
VL3 VL2 VL1 VSS ON OFF ON OFF ON OFF ON OFF
LCD
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 41 LCD drive waveform (1/3 bias, type B)
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit counter.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register, each watchdog timer is set to "FF16." Instructions such as STA, LDM and CLB to generate the write signals can be used. The written data in bits 0 to 5 are not valid, and the above values are set.
When reading the watchdog timer control register is executed, the contents of the high-order 6-bit counter and the STP instruction disable bit (bit 6), and the count source selection bit (bit 7) are read out. When the STP instruction disable bit is "0", the STP instruction is valid. The STP instruction is disabled by writing to "1" to this bit. In this time, when the STP instruction is executed, it is handled as the undefined instruction, the internal reset occurs. This bit cannot be cleared to "0" by program. This bit is "0" after reset. The time until the underflow of the watchdog timer control register after writing to the watchdog timer control register is executed is as follows (when the bit 7 of the watchdog timer control register is "0") ; * at through, frequency/2/4/8 mode (f(XIN)) = 8 MHz): 32.768 ms * at low-speed mode (f(XCIN) = 32 KHz): 8.19s
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog timer starts to count down by writing an optional value in the watchdog timer control register. An internal reset occurs at an underflow of the watchdog timer. Then, reset is released after the reset release time is elapsed, the program starts from the reset vector address. Normally, writing to the watchdog timer control register before an underflow of the watchdog timer is programmed. If writing to the watchdog control register is not executed, the watchdog timer does not operate.
s Note
The watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to release the stop state and in the wait mode. Accordingly, do not underflow the watchdog timer in this time.
Data bus
XCIN "1"
System clock control bit (bit 6) "0"
Watchdog timer H count source selection bit
1/1024
"0"
Watchdog timer L (2) Watchdog timer H (6) "FF16" is set when watchdog timer control register is written to.
1/4 XIN
"1"
Undefined instruction Reset
STP instruction disable bit STP instruction
RESETIN
Reset circuit Wait until reset release
Internal reset
Fig. 42 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register (WDTCON : address 003716)
Watchdog timer H (for read-out of high-order 6 bit) "FF16" is set to watchdog timer by writing to these bits. STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer count source selection bit 0: 1/1024 of system clock 1: 1/4 of system clock
Fig. 43 Structure of Watchdog timer control register
f(XIN)
32msec (at f(XIN)=8MHZ)
Internal reset signal
Watchdog timer detected
Fig. 44 Timing diagram of reset output
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK OUTPUT FUNCTION
A system clock can be output from I/O port P36.The triple function of I/O port, timer 2 output function and system clock output function is performed by the clock output control register (address 001816) and the timer 2 output selection bit of the timer 12 mode register (address 002516). In order to output a system clock from I/O port P36, set the timer 2 output selection bit and bit 0 of the clock output control register to "1". When the clock output function is selected, a clock is output while the direction register of port P36 is set to the output mode. P36 is switched to the port output or the output (timer 2 output and the clock output) except port at the cycle after the timer 2 output control bit is switched.
b7
b0
Clock output control register (CKOUT : address 001816)
P36 clock output control bit 0: Timer 2 output 1: System clock output Not used (returns "0" when read)
Fig. 45 Structure of clock output control register
Timer 2 output control bit
Timer 2 latch (8) Timer 2 (8) 1/2
T
S
Q Q
"0" "1"
T2OUT output edge switch bit
"0"
"1"
P36 clock output control bit P36 latch
P36/T2OUT/
P36 direction register
Timer 2 output selection bit
System clock
b7
b0 Timer 12 mode register (address 002516) T12M Timer 2 output selection bit 0: I/O port 1: Timer 2 output
Fig. 46 Block diagram of Clock output function
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between VCC (min.) and 5.5 V, and the quartz-crystal oscillator should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage meets VIL spec. when a power source voltage passes VCC (min.).
RESET VCC Power source voltage 0V Reset input voltage 0V
Poweron
VIL spec.
RESET
VCC Power source voltage detection circuit
Fig. 47 Reset circuit example
XIN
RESET
Internal reset
Reset address from vector table
Address Data
?
?
?
?
FFFC ADL
FFFD
ADH, ADL
ADH
SYNC XIN : about 8000 cycles
Note 1: The frequency relation of f(XIN) and f() is f(XIN) = 8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 48 Reset sequence
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents (1) Port P0 (2) Port P0 direction register (3) Port P1 (4) Port P1 direction register (5) Port P2 (6) Port P2 direction register (7) Port P3 (8) Port P3 direction register (9) Port P4 (10) Port P4 direction register (11) Port P5 (12) Port P5 direction register (13) Port P6 (14) Port P6 direction register (15) Clock output control register (16) A-D control register (17) Serial I/O1 status register (18) Serial I/O2 status register (19) Timer 1 (20) Timer 2 (21) Timer 3 (22) Timer 4 (23) PWM01 register (24) Timer 12 mode register (25) Timer 34 mode register (26) Compare register (low-order) (27) Compare register (high-order) (28) Timer X (low-order) (29) Timer X (high-order) (30) Timer X (extension) (31) Timer Y (low-order) (32) Timer Y (high-order) (33) Timer X mode register (34) Timer Y mode register 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 001816 001916 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0816 (35) Watchdog timer control register (36) LCD power control register (37) LCD mode register (38) Interrupt edge selection register (39) CPU mode register (40) Interrupt request register 1 (41) Interrupt request register 2 (42) Interrupt control register 1 (43) Interrupt control register 2 (44) Serial I/O1 control register (45) UART1 control register (46) Serial I/O2 control register (47) UART2 control register (48) Oscillation output control register (49) PULL register (50) Key input control register (51) Timer 1234 mode register (52) Timer X control register
Address Register contents 003716 0 0 1 1 1 1 1 1 003816 003916 003A16 0016 0016 0016
003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0FE016 0016 0016 0016 0016 0016
0FE116 1 1 1 0 0 0 0 0 0FE316 0016
0FE416 1 1 1 0 0 0 0 0 0FF016 0FF116 0FF216 0FF316 0FF416 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 FF16 0016
001D16 1 0 0 0 0 0 0 0 001F16 1 0 0 0 0 0 0 0 002016 002116 002216 002316 002416 002516 002616 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 FF16 0116 FF16 FF16 0016 0016 0016 0016 0016 FF16 FF16 0016 FF16 FF16 0016 0016
(53) Timer 12 frequency division selection register 0FF516 (54) Timer 34 frequency division selection register 0FF616 (55) Timer XY frequency division selection register 0FF716 (56) Segment output disable register 0 (57) Segment output disable register 1 (58) Segment output disable register 2 (59) Timer Y mode register 2 (60) Flash memory control register (61) Processor status register (62) Program counter 0FF816 0FF916 0FFA16 0FFB16
0FFE16 0 0 0 0 1 (PS) 1 (PCH) (PCL)
FFFD16 contents FFFC16 contents
X: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 49 Internal status at reset
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 38C2 group has two built-in oscillation circuits; main clock XIN- XOUT and sub-clock XCIN-XCOUT. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feedback resistor exists on-chip. However, an external feedback resistor is needed between XCIN and XCOUT. When the clock signal is supplied from external for the main clock, input the signal to XIN pin and input the inverted-phase signal of XIN to XOUT pin by the external inverter. When the clock signal is supplied from external for the sub-clock, input the signal to XCIN and leave XCOUT open. Immediately after power on, only the XIN oscillation circuit starts oscillating.
s Notes on Clock Generating Circuit
If you switch the mode between through, frequency/2/4, or 8 and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode, set the frequency on condition that f(XIN) > 3f(XCIN).
Oscillation Control (1) Stop Mode
If the STP instruction is executed, the system clock stops at an "H" level, and main clock and sub-clock oscillators stop. In this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. Set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8 bits of timer 2) before the STP instruction. The frequency divider for timer 1 is used for the timer 1 count source, and the output of timer 1 is forcibly connected to timer 2. In this time, bits 0 to 5 of the timer 12 mode register are cleared to "0". The values of the timer 12 frequency divider selection register are not changed. Set the interrupt enable bits of the timer 1 and timer 2 to disabled ("0") before executing the STP instruction. Oscillator restarts When reset occurs or an interrupt request is received, but the system clock is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize.
Frequency Control (1) Frequency/8 Mode
The system clock is the frequency of XIN divided by 8. After reset is released, this mode is selected.
(2) Frequency/4 Mode
The system clock is the frequency of XIN divided by 4.
(3) Frequency/2 Mode
The system clock is the frequency of XIN divided by 2.
(4) Through Mode
The system clock is the frequency of XIN.
(2) Wait Mode
If the WIT instruction is executed, the system clock stops at an "H" level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The system clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
(5) Low-speed Mode
The system clock is the frequency of XCIN divided by 2. In the lowspeed mode, the low-power dissipation operation can be performed when the main clock XIN is stopped by setting the bit 7 of the CPU mode register to "0". In this case, when main clock XIN oscillation is restarted, generate the wait time until the oscillation is stable by program after the bit 7 of the CPU mode register is set to "1".
XCIN
XCOUT
XIN
XOUT
XCIN
XCOUT
XIN
XOUT
Open External oscillation circuit External oscillation circuit, or External pulse
Rfc
CCIN
CCOUT
CIN
COUT
VCC VSS
VCC VSS
Fig. 50 Ceramic resonator circuit
Fig. 51 External clock input circuit
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
System clock control bits
"00,10,11" "01"
P61/XCIN
P62/XCOUT System clock control bits System clock control bits Frequency divider for Timer 1/2 1/2 1/2 1/2
"00,10,11"
"01"
Timer 1 count source selection bits
"01"
Timer 2 count source selection bits
"00"
Timer 1
"00"
"00,10"
Timer 2
"10"
XIN
XOUT
"01,11"
Main clock division ratio selection bits
System clock control bits
"01,10,11" "00"
Frequency/8"00" mode "00" Frequency/4 mode "01" Frequency/2 mode "10" Through mode "11"
System clock control bits
"00,10"
"01,11"
System clock
Q
S R STP instruction WIT instruction
S R
Q
QS R STP instruction
Reset Interrupt disable flag I Interrupt request
Fig. 52 Clock generating circuit block diagram
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
System clock = Main clock f(XIN)
XIN oscillation, XCIN stop CM7=0, CM6=1
Through mode System clock : f(XIN) CM5=1 CM4=1 Frequency/2 mode System clock : f(XIN)/2 CM5=1 CM4=0 Frequency/4 mode System clock : f(XIN)/4 CM5=0 CM4=1 Frequency/8 mode System clock : f(XIN)/8 CM5=0 CM4=0 Reset
CM7="0"
XIN oscillation, XCIN oscillation CM7=1, CM6=1
Through mode System clock : f(XIN) CM5=1 CM4=1 Frequency/2 mode System clock : f(XIN)/2 CM5=1 CM4=0
CM7="1" Frequency/4 mode System clock : f(XIN)/4 CM5=0 CM4=1 Frequency/8 mode System clock : f(XIN)/8 CM5=0 CM4=0
CM6="1"
System clock = Sub-clock f(XCIN)
XIN oscillation, XCIN oscillation CM7=1, CM6=1
b7 CM6="0" b4 CPU mode register (CPUM : address 003B16)
CM5 CM4 : Main clock division ratio selection bits 00: XIN/8 (frequency/8) 01: XIN/4 (frequency/4) 10: XIN/2 (frequency/2) 11: XIN (through mode) CM7 CM6 : System clock control bits 00: XIN stop, XCIN oscillation, system clock = XCIN 01: XIN oscillation, XCIN stop, system clock = XIN 10: XIN oscillation, XCIN oscillation, system clock = XCIN 11: XIN oscillation, XCIN oscillation, system clock = XIN
Low-speed mode System clock : f(XCIN)/2
CM7="1"
XIN stop, XCIN oscillation CM7=0, CM6=0
CM7="0"
Low-power dissipation mode System clock : f(XCIN)/2
Notes 1: When the mode is switched from through or frequency/2/4/8 to the low-speed mode, or the opposite is performed, change CM7 at first, and then, change CM6 after the oscillation of the changed mode is stabilized. 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer and LCD operate in the wait mode. 4: When the stop mode is ended, a delay time can be set by connecting timer 1 and timer 2.
Fig. 53 State transitions of system clock
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Oscillation External Output Function
The 38C2 group has the oscillation external output function to output the rectangular waveform of the clock obtained by the oscillation circuits from P41 and P40. In order to validate the oscillation external output function, set P40 or P41, or both to the output mode (set the corresponding direction register to "1"). The level of the XCOUT external output signal becomes "H" by the P40/P41 oscillation output control bits (bits 0 and 1) of the oscillation output control register (address 0FF016) in the following states; * the function to output the signal from the XCOUT pin externally is selected * the sub-clock (XCIN-XCOUT) is in the oscillating or stop mode. Likewise, the level of the XOUT external output signal becomes "H" by the P40/P41 oscillation output control bits (bits 0 and 1) of the oscillation output control register (address 0FF016) in the following states; * the function to output the signal from the XOUT pin externally is selected * the main clock (XIN-XOUT) is in the oscillating or stop mode.
s Note
When the signal from the XOUT pin or XCOUT pin of the oscillation circuit is input directly to the circuit except this MCU and used, the system operation may be unstabilized. In order to share the oscillation circuit safely, use the clock output from P40 and P41 by this function for the circuits except this MCU.
b7
b0
Oscillation output control register (OSCOUT : address 0FF016) P40/P41 oscillation output control bits b1b0 00: P41, P40 = Normal port 01: P41 = Normal port, P40 = XOUT 10: P41 = Normal port, P40 = XCOUT 11: P41 = XCOUT, P40 = XOUT Not used (return "0" when read) (Do not write to "1")
Fig. 54 Structure of oscillation output control register
P61/XCIN
P62/XCOUT
"01"
"00", "10", "11"
System clock control bits
P41 output latch P40 output latch
System clock control bits
"00", "10", "11" "01"
P41 direction register Oscillation output selection circuit P41/OOUT1 P40/OOUT0 P40 direction register
XIN
XOUT
OSCOUT control
System clock control bits
"01", "10", "11" "00"
Q
S R STP instruction
Reset Interrupt disable flag I Interrupt request
Fig. 55 Block diagram of Oscillation output function
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1." Serial I/O continues to output the final bit from the TXD pin after transmission is completed.
A-D Converter Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 250 kHz (Note) during an A-D conversion. Note: When the frequency divided by 2/4/8 is selected by the AD conversion clock selection bits, the above frequency is multiplied by 2/4/8. Also, when the STP instruction is executed during the A-D conversion, the A-D conversion is stopped immediately, the A-D conversion completion bit is set to "1", and the interrupt request is generated.
Decimal Calculations
* To calculate in decimal notation, set the decimal mode flag (D) to "1," then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing an SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
LCD
When the LCD power input pin VL3 is not used, connect it to VCC.
Timers
* If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * The timers share the one frequency divider to generate the count source. Accordingly, when each timer starts operating, initializing the frequency divider is not executed. Therefore, when the frequency divider is selected for the count source, the delay of the maximum one cycle of the count source is generated until the timer starts counting or the waveform is output from timer starts operating. Also, the count source cannot be checked externally.
Instruction Execution Time
The instruction execution time is obtained by multiplying the number of cycles shown in the list of machine instructions by the period of the internal clock .
Multiplication and Division Instructions
* The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Table 11 Absolute maximum ratings (Mask ROM version) Symbol VCC VI VI VI VI VI VO VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN, CNVSS Output voltage P00-P07, P10-P17, P20-P27 Output voltage COM0-COM3 Output voltage P30-P37, P40-P47, P50-P57, P60-P62 Output voltage XOUT Power dissipation Operating temperature Storage temperature Conditions All voltages are based on Vss. Output transistors are cut off. Ratings -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to VL2 VL1 to VL3 VL2 to 6.5 -0.3 to VCC+0.3 -0.3 to VCC+0.3 -0.3 to VL3+0.3 -0.3 to VL3+0.3 -0.3 to VCC+0.3 -0.3 to VCC+0.3 300 -20 to 85 -40 to 125 Unit V V V V V V V V V V V mW C C
At output port At segment output
Ta = 25C
Recommended Operating Conditions
Table 12 Recommended operating conditions (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol VCC Power source voltage Parameter f() = 8 MHz f() = 2 MHz Low-speed mode Limits Min. 4.0 1.8 1.8 VCC-0.3 0 AVSS 0.7VCC 0.8VCC 0.9VCC 65 VCC-99 VCC - 100 1.5 0 0 0 0 0 VCC VCC VCC VCC VCC VCC 0.3VCC 0.2VCC 0.2VCC 65 VCC-99 100 0.4 Typ. 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 VCC+0.3 Unit V V V V V V V V V V
VSS VREF AVSS VIA VIH VIH VIH
Power source voltage A-D converter reference voltage Analog power source voltage Analog input voltage AN0-AN7 "H" input voltage "H" input voltage "H" input voltage P04-P07, P10-P17, P20-P27, P30, P32, P35, P36, P40-P47, P52, P53, P62 P00-P03, P31, P33, P34, P37, P50, P51, P54-P57, P60, P61 RESET 2.2 V VCC 5.5 V VCC 2.2 V
VIH VIL VIL VIL
"H" input voltage "L" input voltage "L" input voltage "L" input voltage
XIN, XCIN P04-P07, P10-P17, P20-P27, P30, P32, P35, P36, P40-P47, P52, P53, P62 P00-P03, P31, P33, P34, P37, P50, P51, P54-P57, P60, P61, CNVSS RESET 2.2 V VCC 5.5 V VCC 2.2 V
V V V V
VIL
"L" input voltage
XIN, XCIN
V
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 13 Recommended operating conditions (Vcc = 1.8 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) Parameter "H" total peak output current (Note 1) P00-P07, P10-P17, P20-P27, P30-P37 "H" total peak output current (Note 1) P40-P47, P50-P57, P60-P62 "L" total peak output current (Note 1) P00-P07, P10-P17, P20-P27 "L" total peak output current (Note 1) P40-P47, P50, P51, P54-P57, P60-P62 "L" total peak output current (Note 1) P30-P37, P52, P53 "H" total average output current (Note 1) P00-P07, P10-P17, P20-P27, P30-P37 "H" total average output current (Note 1) P40-P47, P50-P57, P60-P62 "L" total average output current (Note 1) P00-P07, P10-P17, P20-P27 "L" total average output current (Note 1) P40-P47, P50, P51, P54-P57, P60-P62 "L" total average output current (Note 1) P30-P37, P52, P53 "H" peak output current (Note 2) P00-P07, P10-P17, P20-P27 "H" peak output current (Note 2) P30-P37, P41-P47, P50-P57, P60-P62 "L" peak output current (Note 2) P00-P07, P10-P17, P20-P27 "L" peak output current (Note 2) P40-P47, P50, P51, P54-P57, P60-P62 "L" peak output current (Note 2) P30-P37, P52, P53 "H" average output current (Note 3) P00-P07, P10-P17, P20-P27 "H" average output current (Note 3) P40-P47, P50-P57, P60-P62 "L" average output current (Note 3) P00-P07, P10-P17, P20-P27 "L" average output current (Note 3) P40-P47, P50, P51, P54-P57, P60-P62 "L" average output current (Note 3) P30-P37, P52, P53 Min. Limits Typ. Max. -20 -20 20 20 110 -10 -10 10 10 90 -1.0 -5.0 10 10 30 -0.5 -2.5 5.0 5.0 15 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is average value measured over 100 ms.
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Recommended operating conditions (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter (4.0 V VCC 5.5 V) (VCC 4.0 V) (4.0 V VCC 5.5 V) (VCC 4.0 V) (2.0 V VCC 5.5 V) (VCC 2.0 V) 32.768 Limits Min. Typ. Max. 4.0 (15VCC-16)/11 8.0 (30VCC-32)/11 8.0 20VCC-32 50 Unit MHz MHz MHz MHz MHz MHz kHz
f(CNTR0) Timer X and Timer Y f(CNTR1) Input frequency (duty cycle 50%) System clock frequency f() f(XIN) f(XCIN) Main clock input oscillation frequency (Note 1) Sub-clock input oscillation frequency (Notes 1, 2)
Notes 1: When the oscillation frequency has a duty cycle of 50%. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Electrical Characteristics
Table 15 Electrical characteristics (Mask ROM version) (Vcc = 4.0 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P17, P20-P27 "H" output voltage P30-P37, P40-P47, P50-P57, P60-P62 Test conditions IOH = -1 mA IOH = -0.25 mA VCC = 1.8 V IOH = -5 mA IOH = -1.5 mA IOH = -1.25 mA VCC = 1.8 V IOL = 10 mA IOL = 3 mA IOL = 2.5 mA VCC = 1.8 V IOL = 15 mA IOL = 4 mA VCC = 1.8 V Min. VCC-2.0 VCC-0.8 VCC-2.0 VCC-0.5 VCC-0.8 2.0 0.5 0.8 2.0 0.8 0.5 0.5 0.5 VI = VCC 5.0 Limits Typ. Max. Unit V V V V V V V V V V V V V A
VOH
VOL
"L" output voltage P00-P07, P10-P17, P20-P27, P40-P47, P50, P51, P54-P57, P60-P62 "L" output voltage P30-P37, P52, P53 Hysteresis INT0-INT2, CNTR0, CNTR1, P00-P03, P54-P57 Hysteresis SCLK1, SCLK2, RxD1, RxD2 Hysteresis RESET "H" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62 "H" input current RESET "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62
VOL
VT+-VTVT+-VTVT+-VTIIH
IIH IIH IIL
IIL IIL
"L" input current RESET "L" input current XIN
VI = VCC VI = VCC VI = VSS Pull-up "OFF" VCC = 5.0 V, VI = VSS Pull-up "ON" VCC = 1.8 V, VI = VSS Pull-up "ON" VI = VSS VI = VSS
5.0 4.0 -5.0 -60 -5.0 -120 -20 -240 -40 -5.0 -4.0
A A A A A A A
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16 Electrical characteristics (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol VRAM ICC Parameter RAM hold voltage Power source current Test conditions When clock is stopped Through mode, Vcc = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors "OFF", A-D converter in operating Through mode, Vcc = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors "OFF", A-D converter stopped Low-speed mode, VCC = 5 V, Ta 55 C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "OFF" Low-speed mode, VCC = 5 V, Ta = 25 C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "OFF" Low-speed mode, VCC = 3 V, Ta 55 C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "OFF" Low-speed mode, VCC = 3 V, Ta = 25 C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "OFF" All oscillation stopped Ta = 25 C (in STP state) Output transistors "OFF" Ta = 85 C Min. 1.8 Limits Typ. 5.1 Max. 5.5 7.5 Unit V mA
1.0
2.0
mA
14
21
A
6
10
A
7
12
A
3
6
A
0.1
1.0 10
A A
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter Characteristics
Table 17 A-D converter characteristics (Mask ROM version) (Vcc = 2.2 to 5.5 V, Vss = AVSS = 0 V, Ta = -20 to 85C, Port state = stopped, unless otherwise noted) Symbol -- -- Parameter Resolution Differencial non-linearity error Non-linearity error Off-set error Full-scale error Differencial non-linearity error Non-linearity error Off-set error Full-scale error Test conditions Min. Limits Typ. Max. 10 1 1 3 5 1 1 2 3 Unit Bits LSB
VCC = VREF = 5 V
Tconv RLADDER IVREF IIA
Conversion time Ladder resistor Reference input current Analog input current
* VCC = VREF = 2.2 V, AD clock frequency = 250 kHz * VCC = VREF = 2.3 V, AD clock frequency = 500 kHz * VCC = VREF = 2.4 V, AD clock frequency = 1 MHz * VCC = VREF = 2.5 V, AD clock frequency = 2 MHz * VCC = VREF = 2.5 V, AD clock frequency = 4 MHz * VCC = VREF = 2.6 V, AD clock frequency = 8 MHz AD conversion clock selection bit :Frequency not divided, 10bitAD mode VREF = 5 V 12 50 35 150
LSB
tc(XIN)121 (Note) 100 200 5.0
s k A A
Note: When "Frequency/2, 4 or 8" is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 2, 4 or 8.
LCD Power Supply Characteristics
Table 18 LCD power supply characteristics (when connecting division resistors for LCD power supply) (Vcc = 1.8 to 5.5 V, Ta = -20 to 85C, unless otherwise noted) Symbol RLCD Parameter Division resistor for LCD power supply (Note) Test conditions RSEL = "10" RSEL = "11" LCD drive timing A LCD circuit division ratio = divided by 1 RSEL = "01" RSEL = "00" LCD circuit division ratio = divided by 2 RSEL = "01" RSEL = "00" LCD circuit division ratio = divided by 4 RSEL = "01" RSEL = "00" LCD circuit division ratio = divided by 8 RSEL = "01" RSEL = "00" LCD drive timing B LCD circuit division ratio = divided by 1 RSEL = "01" RSEL = "00" LCD circuit division ratio = divided by 2 RSEL = "01" RSEL = "00" LCD circuit division ratio = divided by 4 RSEL = "01" RSEL = "00" LCD circuit division ratio = divided by 8 RSEL = "01" RSEL = "00" Min. Limits Typ. 200 5 120 90 150 120 170 150 190 170 150 120 170 150 190 170 190 190 Max. Unit k
Note: The value is the average of each one division resistor.
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing Requirements And Switching Characteristics
Table 19 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0-INT2 input "H" pulse width INT0-INT2 input "L" pulse width Serial I/O1, 2 clock input cycle time (Note) Serial I/O1, 2 clock input "H" pulse width (Note) Serial I/O1, 2 clock input "L" pulse width (Note) Serial I/O1, 2 input setup time Serial I/O1, 2 input hold time Min. 2 125 45 40 250 105 105 80 80 800 370 370 220 100 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When bit 6 of address 0FE016 or 0FE316 is "1" (clock synchronous). Divide this value by four when bit 6 of address 0FE016 or 0FE316 is "0" (UART).
Table 20 Timing requirements 2 (Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Limits Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0-INT2 input "H" pulse width INT0-INT2 input "L" pulse width Serial I/O1, 2 clock input cycle time (Note) Serial I/O1, 2 clock input "H" pulse width (Note) Serial I/O1, 2 clock input "L" pulse width (Note) Serial I/O1, 2 input setup time Serial I/O1, 2 input hold time Min. 2 125 45 40 11000/(15VCC-16) tc(CNTR)/2-20 tc(CNTR)/2-20 230 230 2000 950 950 400 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When bit 6 of address 0FE016 or 0FE316 is "1" (clock synchronous). Divide this value by four when bit 6 of address 0FE016 or 0FE316 is "0" (UART).
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 21 Switching characteristics 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol twH(SCLK) twL(SCLK) td(SCLK-TxD) tV(SCLK-TxD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O1, 2 clock output "H" pulse width Serial I/O1, 2 clock output "L" pulse width Serial I/O1, 2 output delay time Serial I/O1, 2 output valid time Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time CMOS output rising time CMOS output falling time Limits Min. tc(SCLK)/2-30 tc(SCLK)/2-30 (Note 1) (Note 1) -30 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns
140
(Note 2) (Note 2)
10 10
Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is "0." 2: The XOUT, XCOUT pins are excluded.
Table 22 Switching characteristics 2 (Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol twH(SCLK) twL(SCLK) td(SCLK-TxD) tV(SCLK-TxD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O1, 2 clock output "H" pulse width Serial I/O1, 2 clock output "L" pulse width Serial I/O1, 2 output delay time Serial I/O1, 2 output valid time Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time CMOS output rising time CMOS output falling time Limits Min. tC(SCLK)/2-50 tC(SCLK)/2-50 (Note 1) (Note 1) -30 50 50 50 50 Typ. Max. Unit ns ns ns ns ns ns ns ns
350
(Note 2) (Note 2)
20 20
Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is "0." 2: The XOUT, XCOUT pins are excluded.
1k Measurement output pin 100pF Measurement output pin 100pF
CMOS output
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register (address 0EF116 or 0FE416) is " 1." (N-channel open-drain output mode)
Fig. 56 Circuit for measuring output switching characteristics
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC
CNTR0,CNTR1
0.8VCC
tWH(INT)
tWL(INT) 0.2VCC
INT0 to INT2
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
tf
tWL(SCLK) 0.2VCC tsu(RXD-SCLK)
tC(SCLK) tr 0.8VCC
tWH(SCLK)
SCLK1 SCLK2
th(SCLK-RXD)
RXD1 RXD2
td(SCLK-TXD)
0.8VCC 0.2VCC tv(SCLK-TXD)
TXD1 TXD2
Fig. 57 Timing chart
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
64P6N-A
EIAJ Package Code QFP64-P-1414-0.80 HD D
64 49
Plastic 64pin 1414mm body QFP
JEDEC Code - Weight(g) 1.11 Lead Material Alloy 42 MD
e
1
48
b2
I2 Recommended Mount Pad Symbol Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 - - 2.8 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 - 0.8 - 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 - - - - 0.2 - - 0.1 - 0 10 0.5 - - - - 1.3 14.6 - - - - 14.6
HE
E
16
33
17
32
A
L1
F
M
A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME
A2
A1
e y
b
x
L Detail F
64P6Q-A
EIAJ Package Code LQFP64-P-1010-0.50 JEDEC Code - Weight(g) - Lead Material Cu Alloy
c
Plastic 64pin 1010mm body LQFP
MD
e
HD D
64 49
1
48
b2
I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
16
33
17
32
A e F L1
A2
A3
A1
y
b
x y b2 I2 MD ME
x
M
L Detail F
Lp
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 9.9 10.0 10.1 9.9 10.0 10.1 - 0.5 - 11.8 12.0 12.2 11.8 12.0 12.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 - - 0.1 - 0 10 - - 0.225 1.0 - - - - 10.4 - - 10.4
HE
E
c
ME
ME
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38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
* *
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(c) 2000 MITSUBISHI ELECTRIC CORP. 0008 Printed in Japan (ROD) II New publication, effective Aug. 2000. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 1.1 First Edition P53 Table 12 Recommended operating condition
38C2 GROUP DATA SHEET
Revision Description Rev. date 000830 000901
Parameter of VIH, VIL : "XIN" (wrong) "XIN, XCIN" (correct)
(1/1)

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